Jassob's Chalmers org file
My attempt to organize my studies and make my time more efficient.

Table of Contents

These are my current courses, old courses may be found in the archive.

1 Waiting courses (SP2)

1.1 WAITING EDA322 - Digital Design   @study

Table 1: Clock summary at [2018-03-06 tis 12:03]
Headline Time    
Total time 7:01    
EDA322 - Digital Design 7:01    
  Lectures   7:01  
    [50%] Week 1: (16/1-20/1)     2:07
    [0%] Week 2: (23/1-27/1)     0:42
    [33%] Week 5: (13/2-17/2)     3:32

Final Examination: 15 Mar 2017 pm,

Re-exams: June, August

1.1.1 Lectures

  1. IN-PROGRESS [50%] Week 1: (16/1-20/1)
    • [X] Lecture 1: Intro, VHDL basics [16/1 @ 13h15-15h00]
    • [X] Lecture 2: Boolean logic, logic minimization, adders [18/1 @ 15h15-17h00]
    • [ ] Lecture 3: Combinational logic VHDL [19/1 @ 15h15-17h00]
    • [ ] Lecture 4: simple processor, structural VHDL [20/1 @ 10h00-11h45]
  2. IN-PROGRESS [0%] Week 2: (23/1-27/1)
    • [ ] Lecture 5: Sequential circuits [27/1 @ 10h00-11h45]
  3. [0%] Week 3: (30/1-3/2)
    • [ ] Lecture 6: Sequential circuits VHDL [30/1 @ 13h15-15h00]
    • [ ] Lecture 7: Finite State Machines [1/2 @ 15h15-17h00]
    • [ ] Lecture 8: FSM VHDL [5/2 @ 10h00-11h45]
  4. [0%] Week 4: (6/2-10/2)
    • [ ] Lecture 9: Testbenches - VHDL [6/2 @ 13h15-15h00]
    • [ ] Lecture 10: Technologies - ASICs (guest lecture Lars Svensson) [10/2 @ 10h00-11h45]
  5. [33%] Week 5: (13/2-17/2)
    • [X] Lecture 11: Technologies - FPGAs [13/2 @ 13h15-15h00]
    • [ ] Lecture 12: Arithmetic Units [15/2 @ 15h15-17h00]
    • [ ] Lecture 13: VHDL in industry (guest lecture by Jan Andersson, COBHAM Gaisler AB) [17/2 @ 10h00-11h45]
  6. [0%] Week 6: (20/2-24/2)
    • [ ] Lecture 14: System Design and Interfaces [20/2 @ 13h15-15h00]
    • [ ] Lecture 15: Memories and Interconnects [22/2 @ 15h15-17h00]
    • [ ] Lecture 16: Testing & Design for Testing [24/2 @ 10h00-11h45]
  7. [0%] Week 7: (27/2-3/3)
    • [ ] Lecture 17: Pipelining [27/2 @ 13h15-15h00]
    • [ ] Lecture 18: Timing, Delay, Power [29/2 @ 15h15-17h00]
    • [ ] Lecture 19: Asynchronous Sequential Logic [3/3 @ 10h00-11h45]
  8. [0%] Week 8: (6/3-10/3)
    • [ ] Lecture 20: Summary of the lectures [6/3 @ 13h15-15h00]
    • [ ] Lecture TBD: TBD [8/3 @ 15h15-17h00]
    • [ ] Lecture TBD: TBD [10/3 @ 10h00-11h45]

1.1.2 IN-PROGRESS Old exams

2 TODO Master thesis   @study

2.1 Meetings

2.2 Reports

2.2.1 DONE Proposal

2.2.2 DONE Planning report

2.2.3 DONE Half-time report

2.2.4 IN-PROGRESS Final report

Parts left:

  • [ ] Generator evaluation
  • [ ] WhileLang generator

2.3 DONE Writing seminar 1

2.4 DONE Writing seminar 2

2.5 IN-PROGRESS Implementation of prototype 1

Ideas:

  • [ ] Add map of values to DataLang registers, to enable reuse of variables
  • Check tests in Prototype for Palka code generator
  • Add type signature to runTests for "Run all QuickCheck tests"
  • Rename res to r
  • Remove References from Syntax
  • Fix error in types "Move types to their own module"
  • Search for when generateTuple is introduced in Lib.hs
  • Make Number arbitrary precision
  • Add notFoundError to Assign in evalOp "Improve errors somewhat"
  • Add Ref and Deref to holPrint stuff "Split Lib.hs"
  • Select imports from Arrow in Semantics
  • Add resize to "Add stub of evalOp"

2.6 IN-PROGRESS Literature studies

3 IN-PROGRESS History of Science

Course about the history of science and its different interpretations.

Link to Canvas page

3.1 TODO Assignment 1

  • [ ] Do mind map
  • [ ] Write draft
  • [ ] Refine draft

3.2 Assignment 2

3.3 Assignment 3

3.4 Assignment 4

3.5 Assignment 5

4 ARCHIVE   ARCHIVE

Author: Jassob

Created: 2020-04-15 ons 23:16

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